The present invention relates to semiconductor integrated circuits and methods for testing the same.
In recent years, progress in technology for microscaling semiconductor fabrication processes has continued without a letup, and the semiconductor technology has consequently moved into the era of the 90 nm and 65 nm generations. This progress has enabled a complex system conventionally composed of a plurality of LSIs to be integrated on a single silicon chip and realized as a system-on-a-chip. Since transistor integration per unit area and operating frequency have been increased rapidly, a plurality of IP cores having different functions and features can be incorporated into a single chip, thereby realizing a complex high-speed system-on-a-chip.
However, as the number of devices in a semiconductor circuit has increased, the amount of time required to test the circuit has increased. Also, the incorporation of cores having different features requires various types of tests to be performed. As a result, the test cost has been increasing. In addition, since current semiconductor circuits provide high-performance and high-speed operation, it has become difficult to assure high-quality test. Under these situations, system-on-a-chip venders have been studying semiconductor design technology and test techniques for realizing high-quality and low-cost test.
Popular methods conventionally used to test a logic circuit portion in a semiconductor integrated circuit include a scan test method. In order to perform a scan test, it is necessary to form a scan test circuitry in the semiconductor integrated circuit. A typical scan test circuitry is formed using a plurality of scan flip flop circuits in the semiconductor integrated circuit. Each scan flip flop circuit used has an input terminal D, an input terminal DT, a clock terminal CK, an input terminal NT, and a pair of output terminals Q and NQ. At the input terminal D, the flip flop circuit receives a data signal propagated through a circuit block (a combinational circuit). At the input terminal DT, the flip flop circuit receives a scan test signal. The clock terminal CK is used to receive a clock signal. At the input terminal NT, either the signal at the input terminal D or the signal at the input terminal DT is selected as data to be input to the flit flop circuit. From the pair of output terminals Q and NQ, the flip flop circuit outputs data signals.
The scan test circuitry has two modes. These modes are switched according to the value at the terminal NT. Specifically, when the value of the signal at the terminal NT is 1 (this state is called shift mode), the signal at the terminal DT is received by the flip flop circuit as input data. When the value of the signal at the terminal NT is 0 (this state is called capture mode), the signal at the terminal D is received by the flip flop circuit as input data.
The scan test circuitry, which is configured by sequentially connecting the terminals DT and the terminals Q (or NQ) of the scan flip flop circuits with one another, functions as a shift register during shift mode (NT=1) in scan test. An external input terminal, functioning as a scan-test-signal input terminal, is connected to the terminal DT of the scan flip flop circuit provided at the head of the shift register, while an external output terminal, acting as a scan-test-signal output terminal, is connected to the terminal Q or NQ of the scan flip flop circuit disposed in the last stage of the shift register. The terminals CK and NT of the scan flip flop circuits are directly controlled by external input terminals. The scan test circuitry thus configured is also called a scan chain, because the scan flip flop circuits are connected in the form of a chain. The semiconductor integrated circuit may include a plurality of scan chains.
In a typical scan test, an LSI tester supplies scan test signals to the scan-test-signal input terminal. The LSI tester also directly supplies a clock signal and a scan enable signal to the terminals CK and the terminals NT of the scan flip flop circuits, respectively.
While supplying a signal value of 1 as a scan enable signal, the LSI tester applies a clock signal during a period of time in which the number of rising edges of the clock signal is equal to the number of scan flip flop circuits in the scan chain, whereby scan test signals are supplied to all of the scan flip flop circuits forming the scan chain. Thereafter, the scan enable signal is switched to 0, and then one clock is input, whereby signals from the circuit block are captured by the terminals D of the scan flip flop circuits. Then, the scan enable signal is switched again to 1, and a clock signal is applied during a period of time in which the number of rising edges of the clock signal is equal to the number of scan flip flop circuits in the scan chain, whereby the signal values captured by the respective scan flip flop circuits are captured into the LSI tester.
The signal values captured into the LSI tester are then compared with expected values stored beforehand in the LSI tester so as to determine whether or not the captured signal values are appropriate.
In recent years, a logic circuit portion in a semiconductor integrated circuit is being tested using a built-in self-test (BIST) device, instead of performing a typical scan test. The most popular BIST architectures for testing a logic circuit portion include STUMPS (hereinafter, BIST for logic circuit portion will be referred to as “logic BIST”). STUMPS is a BIST architecture based on multiple scan designs. Like a scan test system, a STUMPS architecture uses a scan chain formed in the semiconductor integrated circuit, when performing a test.
The differences between logic BIST and scan test are a test-signal producing circuit and an output-response-signal comparison circuit. In scan testing, test signals are produced and an output-response-signal comparison circuit functions in the manners as described above. On the other hand, in logic BIST, control signals, such as a BIST seizure signal, a clock signal and the like, are applied from an LSI tester, whereby a test signal is produced from a pattern generation circuit included in the semiconductor integrated circuit, and the test signal is then applied to the target circuit to be tested. An output response signal from the circuit under test is input into an output compression circuit, in which the output response signal is converted into compressed data called signature. Finally, the signature is read into the LSI tester so as to be compared with the expected value thereof stored beforehand in the LSI tester, thereby determining whether or not the output signature is appropriate.
The number of devices included in a semiconductor integrated circuit has been increasing recently. Along with this increase, the amount of necessary test data has also been increasing. Furthermore, as technology for microscaling semiconductor fabrication processes has progressed, operation of a system-on-a-chip is adversely affected by small defects, which did not cause any problems before. High-resistance vias, short circuits, crosstalk, and other defects have manifested themselves as delay faults. Therefore, in addition to conventionally needed test data for stack-fault detection, test data for delay-fault detection is also required to be provided. Herein, the amount of test data required in scan test or in logic BIST means the amount of binary data obtained by multiplying the number of bits corresponding to the number of all scan flip flop circuits by the number of captures.
In order to complete a test on a semiconductor integrated circuit (whether typical scan testing or typical logic BIST) in a short time, shift operation has to be performed at high speed for quick setting of test data in the scan chain, so that as many circuit blocks as possible can be tested simultaneously. Since the running cost of an LSI tester is very high, if the tester is used for a long time, the final manufacturing cost of the semiconductor integrated circuit will be affected significantly.
However, in scan test or logic BIST conducted in a semiconductor integrated circuit including numerous devices, high-speed shift operation of the scan chain formed for testing many blocks in the semiconductor integrated circuit causes the semiconductor integrated circuit to consume a significant amount of power, such that normal operation and thus appropriate test cannot be performed. In view of this, it is very important to reduce the power consumption required by shift operation performed in scan test or in logic BIST.
Therefore, Japanese Laid-Open Publication No. 2001-59856, for example, discloses a conventional method to overcome this problem. In this method, when shift operation is performed, output terminals (terminals Q), which transmit data from scan flip flop circuits to a function block (combinational circuit), are fixed, thereby reducing power consumption during the scan test.
FIG. 29 illustrates the configuration of a semiconductor integrated circuit disclosed in the above-mentioned publication. The semiconductor integrated circuit includes a combinational circuit 10 and a plurality of flip flop circuits 11A to 11F. This circuit has the following features. Each of the flip flop circuits 11A to 11F is provided with a terminal SO for transmitting a scan test signal DT to the next flip flop circuit in the scan chain, in addition to a terminal Q for transmitting a data signal D and the scan test signal DT. During shift mode in scan test, the signal values at the terminals Q are kept fixed so that the state within the combinational circuit 10 is not changed.
In previous scan testing circuitry configurations, the signal value at the terminal Q of each scan flip flop circuit varies during shift mode according to a scan test signal applied to the scan flip flop circuit. At this time, many transistors within the combinational circuit simultaneously perform switching, thereby momentarily consuming a considerable amount of power. On the other hand, in the circuit shown in FIG. 29, the signal values at the terminals Q are kept fixed during shift operation, whereby the value at each node within the combinational circuit is fixed, thereby allowing the power consumption to be suppressed during the shift operation.
FIGS. 30 and 31 illustrate the specific flip flop circuit configurations for fixing the output value of the terminal Q, disclosed in the above-mentioned publication.
The flip flop circuit shown in FIG. 30 includes a multiplexer 21, a first latch circuit 22, a second latch circuit 23, an AND circuit 24, and a third latch circuit 25. The multiplexer 21 receives a data signal D and a scan test signal DT and selects as output either the signal D or the signal DT according to the value of a scan enable signal NT. The first latch circuit 22 latches the output signal of the multiplexer 21 according to the inversion signal of a clock signal CLK. The second latch circuit 23 latches the output of the first latch circuit 22 according to the clock signal CLK. The AND circuit 24 receives the clock signal CLK and the inversion signal of a HOLD signal and outputs the result of AND operation of those signals. The third latch circuit 25 latches the output of the second latch circuit 23 according to the output of the AND circuit 24. The output of the second latch circuit 23 functions as a terminal SO, while the output of the third latch circuit 25 acts as an output terminal Q.
In this configuration, when the HOLD signal is 1, the output of the AND circuit 24 is always 0 irrespective of whether the clock signal CLK is 1 or 0. Therefore, at this time, the output Q of the third latch circuit 25 is fixed at the value (0 or 1) held at the previous time regardless of the output value of the first latch circuit 22.
A scan flip flop circuit 11A′ shown in FIG. 31 includes a flip flop circuit 31 and an AND circuit 32. In the flip flop circuit 31, the terminal Q of the conventional scan flip flop circuit 11A of FIG. 30 is configured so as to function as a terminal SO. The AND circuit 32 receives the inversion signal of a HOLD signal and the output of the flip flop circuit 31, and then outputs the result of AND operation of these signals. The output of the AND circuit 32 is the output of the output terminal Q. In this configuration, when the HOLD signal is 1, the output of the AND circuit 32 is always 0 irrespective of whether the output of the flip flop circuit 31 is 1 or 0.
In these conventional techniques, power consumption can be suppressed, but penalties are likely to occur in the circuit area and the speed of performing function. Specific penalties are described in the following.
For example, in the conventional flip flop circuit shown in FIG. 30, area overhead increases by one latch circuit and one AND gate as compared with a typical scan flip flop circuit.
In the conventional flip flop circuit shown in FIG. 31, area overhead increases by one AND gate as compared with a typical scan flip flop circuit. The area of this flip flop circuit is thus smaller than that of the flip flop circuit of FIG. 30 by the one latch circuit. However, in this flip flop circuit, unlike in the flip flop circuit of FIG. 30, the AND gate 32 is provided behind the flip flop circuit 31, causing the signal propagation speed of the output Q to be delayed by the one AND gate.
Therefore, the conventional flip flop circuits shown in FIGS. 30 and 31, which are capable of suppressing power consumption, have disadvantages in that the circuit area increases and the operation speed decreases.